The invention relates generally to semiconductor devices and integrated circuit fabrication and, in particular, to structures for field-effect transistors and methods for fabricating a structure for field-effect transistors.
Complementary-metal-oxide-semiconductor processes may be used to build a combination of p-type and n-type field-effect transistors that are used to construct, for example, logic cells. Field-effect transistors generally include a channel region, a source, a drain, and a gate electrode. When a control voltage exceeding a characteristic threshold voltage is applied to the gate electrode, carrier flow occurs in the channel region between the source and drain to produce a device output current.
Field-effect transistors fabricated using semiconductor-on-insulator technologies may exhibit certain performance improvements in comparison with comparable field-effect transistors built directly in a bulk silicon substrate. Generally, a silicon-on-insulator (SOI) wafer includes a thin device layer of semiconductor material, a substrate, and a thin buried insulator layer, such as a buried oxide layer, physically separating and electrically isolating the device layer from the substrate. Contingent on the thickness of the device layer, a field-effect transistor may operate in a fully-depleted mode (FDSOI) in which the channel region in extends fully across the device layer to the buried insulator layer when typical control voltages are applied to the gate electrode.
Despite the advantages afforded by silicon-on-insulator technologies, switching delay and standby leakage are concerns for FDSOI logic cells when the field-effect transistors are operating in a fully-depleted mode. In addition, dual-gate dynamic switching of FDSOI logic cells cannot be achieved due to an inability to share back gates between the field-effect transistors constituting a logic cell.
Improved structures for field-effect transistors and methods for fabricating a structure for field-effect transistors are needed.